Ultra-Low Power and High-Throughput SRAM Design to Enhance AI Computing Ability in Autonomous Vehicles

Power consumption and data processing speed of integrated circuits (ICs) is an increasing concern in many emerging Artificial Intelligence (AI) applications, such as autonomous vehicles Internet Things (IoT). Existing state-of-the-art SRAM architectures for AI computing are highly accurate can provide high throughput. However, these SRAMs have problems that they consume power occupy a large area to accommodate complex models. A carbon nanotube field-effect transistors (CNFET) device has been reported potential candidates devices requiring ultra-low high-throughput due their satisfactory carrier mobility symmetrical, good subthreshold electrical performance. Based on the CNFET FinFET device’s performance, we propose novel 8T circumvent throughput issues Intelligent computation vehicles. We two types SRAMs, P-Latch N-Access (PLNA) structure single-ended (SE) structure, compare performance with existing terms speed. In CNFET, higher tube fin numbers lead operating number tubes fins larger more consumption. Therefore, optimize by reducing without compromising memory circuit power. Most importantly, decoupled reading writing our new cell offers better low-power operation stacking part, well achieving readability writability, while offering read Static Noise Margin (SNM) free because isolated path, greater pull up ratio. addition, proposed show even delay when combine them collaborated voltage sense amplifier independent component. The PLNA save 96%, SE saves around 99% compared model, model.